1. Field of the Invention
The present invention relates to voltage controlled variable capacitance devices which have a plurality of varactor elements, and more particularly to a voltage controlled variable capacitance device which allows for selecting a voltage—capacitance characteristic.
2. Description of the Related Art
Voltage controlled variable capacitance devices have been conventionally used to control the oscillation frequency of the LC-VCO (Voltage Controlled Oscillator). In general, the voltage controlled variable capacitance device employs a MOS-type varactor element.
FIG. 1 is a cross-sectional view illustrating a conventional voltage controlled variable capacitance device. The conventional voltage controlled variable capacitance device shown in FIG. 1, which is incorporated into a semiconductor integrated circuit, employs a MOS-type varactor element. As shown in FIG. 1, the voltage controlled variable capacitance device is provided with a P type substrate 1, on a surface of which formed is an N well 2. The N well 2 is formed when the N well of a P channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in the semiconductor integrated circuit having the varactor element.
On the N well 2, there is provided a gate insulating film 11, while a polysilicon layer 9 is provided as an electrode on the gate insulating film 11. The polysilicon layer 9 is connected to a gate terminal 7. The gate insulating film 11 is formed, e.g., at the same time as the gate insulating film of an N channel MOSFET is formed, while the polysilicon layer 9 is formed, e.g., at the same time as the gate electrode of an N channel MOSFET is formed.
In addition, the N well 2 has N+ diffusion layers 3 formed at two positions in the surface thereof. The N+ diffusion layers 3 are formed so as to sandwich the polysilicon layer 9 when viewed in a direction perpendicular to the surface of the P type substrate 1 (hereinafter simply referred to as the vertical direction). The N+ diffusion layers 3 are formed at the same time as the source/drain of the N channel MOSFET is formed. The N+ diffusion layers 3 are connected to an S/D terminal 8. In this manner, the N well 2, the N+ diffusion layers 3, the gate insulating film 11, and the polysilicon layer 9 form the varactor element.
In this conventional voltage controlled variable capacitance device, a voltage applied between the gate terminal 7 and the S/D terminal 8 is varied, thereby allowing the capacitance between the N well 2 and the polysilicon layer 9 to be varied. That is, when a positive potential is applied to the gate terminal 7 and a negative potential to the S/D terminal 8 to provide a sufficiently high voltage between both the terminals, electrons serving as carriers are collected near the gate insulating film 11 in the N well 2, placing the varactor element in an accumulation state. As a result, the varactor element becomes generally equal in capacitance to the gate insulating film 11 or to its maximum value. On the other hand, varying the gate terminal 7 toward a negative potential will cause a depletion layer to be formed immediately under the polysilicon layer 9 in the N well 2, and the extension of the depletion layer decreases the capacitance of the varactor element. A sufficiently lowered potential at the gate terminal 7 will drive the extension of the depletion layer into saturation. This allows no more decrease in capacitance and thus its minimum value to be reached.
As described above, the voltage controlled variable capacitance device employing the varactor element provides an advantage that it can be formed at the same time in a step of forming the N channel and P channel MOSFET in a semiconductor integrated circuit, without modifying the fabrication process of the semiconductor integrated circuit or adding a new process thereto.
However, the conventional voltage controlled variable capacitance device has the following problems. That is, the MOS varactor element is formed in the MOSFET fabrication process at the same time as the MOSFET and thus has the characteristics determined by the conditions for forming the MOSFET. However, when the varactor element is used to control the oscillation frequency of the VCO, it is preferable to optimally adjust the dependence of the gate-substrate capacitance on voltage, i.e., the C-V characteristic in accordance with the characteristics required of a circuit such as the VCO incorporated into the voltage controlled variable capacitance device. For example, a steep curve (C-V curve) showing the correlation between voltage and capacitance would make it difficult to control the oscillation frequency of the VCO. In addition, an increase in the ratio between the maximum and minimum capacitance (hereinafter referred to as the capacitance ratio) would provide an advantage of increasing the variable frequency range of the VCO. However, an excessively increased capacitance ratio would require such a transistor to be used as a transistor constituting the VCO, the transistor having an increased dependence of drain current on gate voltage (gm), resulting in an increase in phase noise or fluctuation in oscillation frequency.
For example, a method of varying the impurity concentration of the N well 2 shown in FIG. 1 is available only to vary the C-V characteristic of the voltage controlled variable capacitance device. FIG. 2 is a graph showing the C-V characteristic of a varactor element, the horizontal axis representing the gate—SD voltage and the vertical axis representing the gate—SD capacitance, with the impurity concentration of the N well 2 (see FIG. 1) being varied in the range of 1×1017 to 1×1018 cm−3. As shown in FIG. 2, increasing the impurity concentration of the N well 2 from 1×1017 to 1×1018 cm−3 causes the C-V curve to vary in the direction shown by arrow 31.
As described above, it is possible to increase the impurity concentration of the N well to thereby vary the C-V characteristic of the varactor element, for example, to provide a more gradual C-V curve. However, to optimally control the impurity concentration of the N well, an extra process is required for injecting an impurity to the N well, whereby the N well cannot be formed at the same time as the N well of the P channel MOSFET is formed. Otherwise, a modification would have to be made to the fabrication process of the P channel MOSFET, leading to a change in characteristic of the P channel MOSFET.
On the other hand, such a conventional technique is also disclosed in, e.g., Japanese Patent Laid-Open Publication No. 2002-43842, in which voltage drop means and a plurality of varactor elements are provided to allow the voltage drop means to generate multiple types of voltages, which were in turn applied to the varactor elements to thereby enable the ratio of change in capacitance to be set to a given value.
However, the aforementioned conventional technique has the following problems. The technique described in Japanese Patent Laid-Open Publication No. 2002-43842 requires the voltage drop means to be provided, thus raising a problem that the circuit becomes complicated in configuration and increased in size. Additionally, the circuit operates only with a sufficiently high control voltage, thus raising a problem of running counter to the attempt of lowering the operating voltage of the semiconductor integrated circuit.